1) Which among the below mentioned functions does not belong to the category of alternate functions usually performed by Port 3 (Pins 10-17)?
a. External Interrupts
b. Internal Interrupts
c. Serial Ports
d. Read / Write Control signals
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2) What is the constant activation rate of ALE that is optimized periodically in terms of an oscillator frequency?
a. 1 / 8
b. 1 / 6
c. 1 / 4
d. 1 / 2
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3) Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution?
a. ALE
b. PSEN
c. EA
d. All of the above
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4) Which memory allow the execution of instructions till the address limit of 0FFFH especially when the External Access (EA) pin is held high?
a. Internal Program Memory
b. External Program Memory
c. Both a & b
d. None of the above
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5) Which value of disc capacitors is preferred or recommended especially when the quartz crystal is connected externally in an oscillator circuit of 8051?
a. 10 pF
b. 20 pF
c. 30 pF
d. 40 pF
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6) Why are the resonators not preferred for an oscillator circuit of 8051?
a. Because they do not avail for 12 MHz higher order frequencies
b. Because they are unstable as compared to quartz crystals
c. Because cost reduction due to its utility is almost negligible in comparison to total cost of microcontroller board
d. All of the above
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7) Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level?
a. HMOS
b. CHMOS
c. CMOS
d. All of the above
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8) Which signal from CPU has an ability to respond the clocking value of D- flipflop (bit latch) from the internal bus?
a. Write-to-Read Signal
b. Write-to-Latch Signal
c. Read-to-Write Signal
d. Read-to-Latch Signal
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9) Which among the below mentioned statements are precisely related to quasi-bidirectional port?
a. Fixed high pull-up resistors are internally connected
b. Configuration in the form of input pulls the port at higher position whereas they get pulled lower when configured as a source current
c. It is possible to drive the pin as output at any duration when FET gets turned OFF for an input function
d. Upper pull-up FET is always OFF with the provision of 'open-drain' output pin for normal operation of port
a. A, B, C, D
b. A, B & C
c. A & B
d. C & D
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10) What happens when the pins of port 0 & port 2 are switched to internal ADDR and ADDR / DATA bus respectively while accessing an external memory?
a. Ports cannot be used as general-purpose Inputs/Outputs
b. Ports start sinking more current than sourcing
c. Ports cannot be further used as high impedance input
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: Ports cannot be used as general-purpose Inputs/Outputs
Explanation:
No explanation is available for this question!
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11) The upper 128 bytes of an internal data memory from 80H through FFH usually represent _______.
a. general-purpose registers
b. special function registers
c. stack pointers
d. program counters
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12) What is the bit addressing range of addressable individual bits over the on-chip RAM?
a. 00H to FFH
b. 01H to 7FH
c. 00H to 7FH
d. 80H to FFH
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13) What is the divisional range of program memory for internal and external memory portions respectively when enable access pin is held high (unity)?
a. 0000H - 0FFFH & 1000H - FFFFH
b. 0000H - 1000H & 0FFFH - FFFFH
c. 0001H - 0FFFH & 01FFH - FFFFH
d. None of the above
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14) Consider the following statements. Which of them is/are correct in case of program execution related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status of EA pin is high (1)
b. External Program memory execution takes place from 0000H through 0FFFH only when the status of EA pin is low (0)
c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held low (0)
d. Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held high (1)
a. A & C
b. B & D
c. A & B
d. Only A
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15) How does the processor respond to an occurrence of the interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
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16) Which address/location in the program memory is supposed to get occupied when CPU jump and execute instantaneously during the occurrence of an interrupt?
a. Scalar
b. Vector
c. Register
d. All of the above
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17) Which location specify the storage/loading of vector address during the interrupt generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
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18) Match the following :
a. ISS ----------------------------- 1. Monitors the status of interrupt pin
b. IER ----------------------------- 2. Allows the termination of ISS
c. RETI --------------------------- 3. MCS-51 Interrupts Initialization
d. INTO -------------------------- 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
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19) What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt?
a. Edge-Triggering
b. Level Triggering
c. Both a & b
d. None of the above
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20) Which among the below mentioned reasons is/are responsible for the generation of Serial Port Interrupt?
a. Overflow of timer/counter 1
b. High to low transition on pin INT1
c. High to low transition on pin INT0
d. Setting of either TI or RI flag
a. A & B
b. Only B
c. C & D
d. Only D
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21) What is the counting rate of a machine cycle in correlation to the oscillator frequency for timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
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22) Which special function register play a vital role in the timer/counter mode selection process by allocating the bits in it?
a. TMOD
b. TCON
c. SCON
d. PCON
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23) How many machine cycle/s is/are executed by the counters in 8051 in order to detect '1' to '0' transition at the external pin?
a. One
b. Two
c. Four
d. Eight
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24) Which bit must be set in TCON register in order to start the 'Timer 0' while operating in 'Mode 0'?
a. TR0
b. TF0
c. IT0
d. IE0
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25) Which among the following control/s the timer1 especially when it is configured as a timer in mode'0', where gate and TR1 bits are attributed to be '1” in TMOD register?
a. TR1
b. External input at (INT1)
c. TF1
d. All of the above
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26) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE enhancing the program counter to jump to another vector location?
a. Mode 0
b. Mode 1
c. Mode 2
d. Mode 3
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27) Consider the below generated program segment for initializing Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0
SJMP $
Which among the below mentioned program segments represent the correct code?
a. MOV SP, # 54 H
MOV TCON ,# 0010 0000 C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, # 54H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $
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Answer
Explanation
Related Ques
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ANSWER: MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
Explanation:
No explanation is available for this question!
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28) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an auto-reload mode (Mode 2) operation of the timer?
a. 125 μs
b. 250 μs
c. 256 μs
d. 1200 μs
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29) Which among the below mentioned sequence of program instructions represent the correct chronological order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B
2. MOV TL0, # 06H
3. MOV TH0, # 06H
4. SETB TR0
5. CPL p1.0
6. ORG 0000H
a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
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30) Why is it not necessary to specify the baud rate to be equal to the number of bits per second?
a. Because each bit is preceded by a start bit & followed by one stop bit
b. Because each byte is preceded by a start byte & followed by one stop byte
c. Because each byte is preceded by a start bit & followed by one stop bit
d. Because each bit is preceded by a start byte &followed by one stop byte
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Answer
Explanation
Related Ques
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ANSWER: Because each byte is preceded by a start bit & followed by one stop bit
Explanation:
No explanation is available for this question!
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