1) From where do the voltage noise get induced into the logic circuit?
a. From a gate output to load
b. From the connecting wires used between two gates
c. Both a and b
d. None of the above
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2) If a high logic output drives a logic circuit input, which among the below specified reasons will be responsible in causing a voltage drop into an invalid state?
a. Positive noise spike greater than VNL
b. Positive noise spike less than VNL
c. Negative noise spike greater than VNH
d. Negative noise spike less than VNH
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3) What is the standard percentage level used for measuring the propagation delay between the points corresponding to the inverter diagram shown below?
a. 20%
b. 50%
c. 70%
d. 100%
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4) What should be the value of input voltage for an efficient operation of a logic circuit by avoiding the conditions of invalid voltage levels?
a. Lower than VIL (max)
b. Higher than VIH (min)
c. Both a and b
d. None of the above
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5) Which is the correct sequential order of operational steps executed in the combinational logic circuits?
A. Operation of combinational gates over the inputs
B. Acceptance of n-different inputs
C. Generation of 'm' different outputs as per the required level
a. A, B, C
b. A, C, B
c. B, A, C
d. C, A, B
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6) For the given truth-table, what is the logical expression in the standard SOP form?
a. Y = Σm (0,1)
b. Y = Σm (1,2)
c. Y = Σm (2,3)
d. Y = Σm (3,4)
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7) Which is the correct boolean expression for the logic circuit given below?
a. Y = (A.B) (A+ B) (A+C)
b. Y = (A.B) / (A + B) (A + C)
c. Y = (A.B) / (A + B) (A + C)
d. Y = (A.B)(A + B)(A+C)
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8) Which code is used for labeling the cells of K-map?
a. Binary
b. Gray
c. BCD
d. ASCII
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9) Which parameters are generated by the ripple carry propagation in the addition process of parallel adder?
A. Propagation delay
B. Time delay
C. Carry delay
D. Speed delay
a. A & B
b. B & C
c. A & C
d. C & D
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10) Which number/ code is added to an incorrect result obtained in BCD addition for correction purpose?
a. One (0001)
b. Three (0011)
c. Six (0110)
d. Nine (1001)
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11) According to the truth-table given below, the output case for one-bit comparator is __________
a. A < B
b. A > B
c. A = B
d. None of the above
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12) How many arithmetic operations can be performed by Arithmetic Logic Unit?
a. 10
b. 12
c. 16
d. 32
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13) For the schematic shown below, if the rectangular signal is applied in the form of clock signal to edge-triggered flip-flop, then where will be the change in its output?
a. Only at rising edge
b. Only at falling edge
c. Either at rising edge or falling edge
d. Neither at rising edge nor at falling edge
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14) In delay flip-flop, _______ after the propagation delay.
a. Input follows input
b. Input follows output
c. Output follows input
d. Output follows output
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15) Which among the following statements is correct for the triggering associated with bistable elements?
a. Latch is level-triggered flip-flop
b. Latch is edge-triggered flip-flop
c. Flip-flop is edge-triggered latch
d. Flip-flop is not edge sensitive
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16) T flip- flop finds its application in the form of frequency division since it divides the clock frequency by ________
a. 2
b. 4
c. 2n - 1
d. 4n - 1
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17) Which is the correct sequence of operations to be necessarily performed in the resistance welding application of ring counter?
a. Hold, Squeeze, Weld, Off
b. Squeeze, Hold, Weld, Off
c. Weld, Squeeze, Hold, Off
d. Off, Squeeze, Hold, Weld
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18) For a ring counter, the number of output states are always equal to ______
a. Number of input states
b. Number of clock pulses
c. Number of registers
d. Number of flip flops
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19) On the second falling edge of clock in ring counter, if the generated output of second clock pulse is ' 0100', what will be the output after the fourth clock pulse?
a. 1000
b. 0001
c. 0010
d. 0000
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20) If a complete sequence is detected, what will be the output of a sequence detector?
a. 1
b. 0
c. Both a and b
d. None of the above
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21) If the output of two-bit asynchronous binary up counter using T flip flops is '00' at reset condition, then what output will be generated after the fourth negative clock edge?
a. 00
b. 01
c. 10
d. 11
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22) On which factor/s does the clock pulse frequency of a counter depend/s for its reliable operation?
a. Number of flip flops
b. Width of strobe pulse
c. Propagation delay
d. All of the above
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23) Which flip flops serve to be the fundamental building blocks of counters?
a. S-R flip flops
b. J-K flip flops
c. T flip flops
d. D flip flops
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24) Why is the extent of propagation delay in synchronous counter much lesser than that of asynchronous counter?
a. Due to clocking of all flip flops at the same instant
b. Due to increase in number of states
c. Due to absence of connection between output of preceding flip flop and clock of next one
d. Due to absence of mode control operation
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Answer
Explanation
Related Ques
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ANSWER: Due to clocking of all flip flops at the same instant
Explanation:
No explanation is available for this question!
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25) Where are signals received from, at the output decoder in generalized form of Mealy circuit?
A. Input of memory elements
B. Output of memory elements
C. External inputs
D. External outputs
a. A & D
b. B & C
c. B & D
d. A & C
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26) Consider the state equation given below. If R.H.S of an equation is zero, then what would be the value of L.H.S (next state) after the application of a clock pulse?
QA(n + 1) = (QA QB + QA QB) x + QA QB
a. Zero
b. Infinity
c. QA QB x
d. QA QB x
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27) Which among the following state machine notations are generated outside the sequential circuits?
a. Input variables
b. Output variables
c. State variables
d. Excitation variables
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28) Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits?
a. State Reduction
b. State Minimization
c. State Assignment
d. State Evaluation
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29) Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?
a. PLCC
b. QFP
c. PGA
d. BGA
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30) What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view?
a. Input operation
b. Tristate output operation
c. Bi-directional I/O pin access
d. All of the above
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31) What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA?
A. Propagation delay will increase
B. FPGA area will increase
C. Wastage of logic modules will not be prevented
D. Number of interconnected paths in device will decrease
a. A & B
b. C & D
c. A & D
d. B & C
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32) In JTAG programming, JTAG stands for ________
a. Joint Texture Analysis Group
b. Joint Technique Aided Group
c. Joint Testing Array Group
d. Joint Test Action Group
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33) Which operations are likely to get performed by the Content Accessible Memories (CAM) in addition to read/write operations executed by conventional memories?
a. Association
b. Distribution
c. Commutation
d. Identification
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34) Which among the following techniques is used by EPROM for erasing purpose?
a. Force Convection
b. Ultraviolet Radiation
c. Photo-conduction
d. None of the above
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35) Which among the following specifies the minimum amount of time necessary for data validation after the termination of the write pulse?
a. Write pulse time
b. Write release time
c. Data set up time
d. Data hold up time
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36) Which parameter of read cycle timing characteristics defines the maximum time delay between the beginning of read pulse and output buffers arriving at active state from Hi-z condition?
a. Read to output valid time
b. Read to output active time
c. Access time
d. Output tristate from read time
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37) Which among the following is the correct way of entity representation for the two input NAND gate shown below?
a. NAND 5 entity is
port (A, B : input;
C: output);
NAND 5 end;
b. entity NAND5 is
port (A, B : in bit;
C: out bit);
end NAND 5;
c. Entity: NAND5
port(Inputs: A, B;
Output : C);
end;
d. entity : NAND5
port( inbit : A,B),
( outbit: C);
end.
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Answer
Explanation
Related Ques
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ANSWER: entity NAND5 is
port (A, B : in bit;
C: out bit);
end NAND 5;
Explanation:
No explanation is available for this question!
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38) Which type of architectural modeling style describes the internal design details in the form of a set representing the interconnected components?
a. Dataflow
b. Behavioral
c. Structural
d. Mixed
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39) Dataflow style of architectural modeling is represented as a set of ___________ assignment statements.
a. Sequential
b. Concurrent
c. Random
d. Combinational
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40) How are the design specifications represented in the behavioral modeling style of VHDL?
a. Boolean equation
b. Truth table
c. Logical diagram
d. State diagram
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